vishay siliconix si4830ady document number: 72021 s09-0868-rev. g, 18-may-09 www.vishay.com 1 dual n-channel 30-v (d-s) mosfet with schottky diode features ? halogen-free according to iec 61249-2-21 definition ? little foot ? plus schottky ? si4830dy pin compatible ? pwm optimized ? 100 % r g te s t e d ? compliant to rohs directive 2002/95/ec applications ? asymmetrical buck-boost dc/dc converter product summary v ds (v) r ds(on) ( )i d (a) 30 0.022 at v gs = 10 v 7.5 0.030 at v gs = 4.5 v 6.5 schottky product summary v ds (v) v sd (v) diode forward voltage i f (a) 30 0.50 at 1 a 2.0 notes: a. surface mounted on 1" x 1" fr4 board. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol 10 s steady state unit drain-source voltage v ds 30 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) a t a = 25 c i d 7.5 5.7 a t a = 70 c 6.0 4.6 pulsed drain current i dm 30 continuous source cu rrent (diode conduction) a i s 1.7 0.9 maximum power dissipation a t a = 25 c p d 2.0 1.1 w t a = 70 c 1.3 0.7 operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter mosfet schottky symbol typ. max. typ. max. unit maximum junction-to-ambient a t 10 s r thja 52 62.5 53 62.5 c/w steady state 93 110 93 110 maximum junction-to-foot (drain) steady state r thjf 35 40 35 40 s 1 /d 2 d 1 g 1 d 1 s 2 g 2 so- 8 5 6 7 8 top v ie w 2 3 4 1 n -channel mosfet d 1 g 1 s 1 n -channel mosfet d 2 g 2 s 2 schottky diode s 1 /d 2 s 1 /d 2 orderin g information: si4 8 30ady -t1-e3 (lead (p b )-free) si4 8 30ady -t1-ge3 (lead (p b )-free and halogen-free)
www.vishay.com 2 document number: 72021 s09-0868-rev. g, 18-may-09 vishay siliconix si4830ady notes: a. guaranteed by design, not subject to production testing. b. pulse test; pulse width 300 s, duty cycle 2 %. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. mosfet specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. a max. unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.4 3.0 v gate-body leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v ch-1 1 a ch-2 100 v ds = 30 v, v gs = 0 v, t j = 85 c ch-1 15 ch-2 2000 on-state drain current b i d(on) v ds = 5 v, v gs = 10 v 20 a drain-source on-state resistance b r ds(on) v gs = 10 v, i d = 7.5 a 0.017 0.022 v gs = 4.5 v, i d = - 6.5 a 0.024 0.030 forward transconductance b g fs v ds = 15 v, i d = 7.5 a 19 s diode forward voltage b v sd i s = 1 a, v gs = 0 v ch-1 0.75 1.2 v ch-2 0.47 0.5 dynamic a total gate charge q g v ds = 15 v, v gs = 4.5 v, i d = 7.5 a 711 nc gate-source charge q gs 2.9 gate-drain charge q gd 2.5 gate resistance r g 0.5 1.5 2.4 tu r n - o n d e l ay t i m e t d(on) v dd = 15 v, r l = 15 i d ? 1 a, v gen = 10 v, r g = 6 915 ns rise time t r 10 17 turn-off delaytime t d(off) 19 30 fall time t f 915 source-drain reverse recovery time t rr i f = 1.7 a, di/dt = 100 s ch-1 35 55 ch-2 32 55 schottky specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit forward voltage drop v f i f = 1.0 a 0.47 0.50 v i f = 1.0 a, t j = 125 c 0.36 0.42 maximum reverse leakage current i rm v r = 30 v 0.004 0.100 ma v r = 30 v, t j = 100 c 0.7 10 v r = - 30 v, t j = 125 c 3.0 20 junction capacitance c t v r = 10 v 50 pf
document number: 72021 s09-0868-rev. g, 18-may-09 www.vishay.com 3 vishay siliconix si4830ady mosfet typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current gate charge 0 5 10 15 20 25 30 0246 8 10 v gs = 10 v thr u 5 v v ds - drain-to-so u rce v oltage ( v ) -) a ( t n e r r u c n i a r d i d 3 v 4 v -( ) e c n a t s i s e r - n o r ) n o ( s d 0.000 0.010 0.020 0.030 0 . 040 0 5 10 15 20 25 30 i d - drain c u rrent (a) v gs = 10 v v gs = 4.5 v 0 2 4 6 8 10 0 3 6 9 12 15 v ds = 15 v i d = 7.5 a -) v ( e g a t l o v e c r u o s - o t - e t a g q g - total gate charge (nc) v s g transfer characteristics capacitance on-resistance vs. junction temperature 0 5 10 15 20 25 30 012345 t c = 125 c - 55 c 25 c v gs - gate-to-so u rce v oltage ( v ) -) a ( t n e r r u c n i a r d i d 0 240 4 8 0 720 960 1200 0 5 10 15 20 25 30 v ds - drain-to-so u rce v oltage ( v ) c rss c- ) f p ( e c n a t i c a p a c c oss c iss 0.6 0. 8 1.0 1.2 1.4 1.6 1 . 8 - 50 - 25 0 25 50 75 100 125 150 v gs = 10 v i d = 7.5 a t j - j u nction temperat u re (c) ) d e z i l a m r o n ( - e c n a t s i s e r - n o r ) n o ( s d
www.vishay.com 4 document number: 72021 s09-0868-rev. g, 18-may-09 vishay siliconix si4830ady mosfet typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 t j = 150 c 20 10 0.1 v sd - s o u rce-to-drain v oltage ( v ) -) a ( t n e r r u c e c r u o s i s 1 t j = 25 c - 0. 8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a ) v ( e c n a i r a v v ) h t ( s g t j - temperat u re (c) on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.00 0.01 0.02 0.03 0.04 0.05 0 . 06 0246 8 10 i d = 7.5 a -( ) e c n a t s i s e r - n o r ) n o ( s d v gs - gate-to-so u rce v oltage ( v ) 0 60 100 20 40 time (s) 8 0 1 10 10 -1 10 -2 10 -3 po w er ( w ) safe operating area, junction-to-foot 100 1 0.1 1 10 100 0.01 10 100 ms 0.1 t c = 25 c single p u lse 1 s 10 s dc 10 ms 1 ms limited b y r ds(on) * v ds - drain-to-so u rce v oltage ( v ) * v ds > minim u m v gs at w hich r ds(on) is specified i d - drain c u rrent (a)
document number: 72021 s09-0868-rev. g, 18-may-09 www.vishay.com 5 vishay siliconix si4830ady mosfet typical characteristics 25 c, unless otherwise noted normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 1 10 600 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) e v i t c e f f e d e z i l a m r o n t n e i s n a r t e c n a d e p m i l a m r e h t 1. d u ty cycle, d = 2. per unit base = r thja = 93 c/ w 3. t jm ? t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 1 10 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) e v i t c e f f e d e z i l a m r o n t n e i s n a r t e c n a d e p m i l a m r e h t
www.vishay.com 6 document number: 72021 s09-0868-rev. g, 18-may-09 vishay siliconix si4830ady schottky typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72021 . reverse current vs. junction temperature 0 25 50 75 100 125 150 20 10 0.0001 -) a m ( t n e r r u c e s r e v e r i r t j - temperat u re (c) 30 v 24 v 0.001 0.01 0.1 1 forward voltage drop 0.0 0.3 0.6 0.9 1.2 1.5 10 1 -) a ( t n e r r u c d r a w r o f i f v f - for w ard v oltage drop ( v ) t j = 150 c t j = 25 c capacitance v ds - drain-to-so u rce v oltage ( v ) c -) f p ( e c n a t i c a p a c 0 40 8 0 120 160 200 0 6 12 1 8 24 30 c oss
vishay siliconix package information document number: 71192 11-sep-06 www.vishay.com 1 dim millimeters inches min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all le a d s q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (g a ge pl a ne) s oic (narrow): 8-lead jedec p a rt n u m b er: m s -012 s
vishay siliconix trenchfet ? power mosfets application note 808 mounting little foot ? , so-8 power mosfets application note document number: 70740 www.vishay.com revision: 18-jun-07 1 wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footpr int of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawin g access for vishay siliconix mosfets, ( http://www.vishay.com/ppg?72286 ), for the basis of the pad design for a little foot so-8 power mosfet. in converting this recommended minimum pad to the pad set for a power mosfet, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. in the case of the so-8 p ackage, the thermal connections are very simple. pins 5, 6, 7, and 8 are the drain of the mosfet for a single mosfet package and are connected together. in a dual package, pi ns 5 and 6 are one drain, and pins 7 and 8 are the other drain. for a small-signal device or integrated circuit, typical co nnections would be made with traces that are 0.020 inches wi de. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copp er may be adequate to carry the current required for the a pplication, but it presents a large thermal impedance. also , heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources wh en looking at heat spread on the pc board. figure 1. single mosfet so-8 pad pattern with copper spreading figure 2. dual mosfet so-8 pad pattern with copper spreading the minimum recommended pad patterns for the single-mosfet so-8 with copp er spreading (figure 1) and dual-mosfet so-8 with copper spreading (figure 2) show the starting point for utilizing th e board area available for the heat-spreading copper. to creat e this pattern, a plane of copper overlies the drain pins . the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat fr om the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. these patterns use all the available area underneath the body for this purpose. since surface-mounted packag es are small, and reflow soldering is the most comm on way in which these are affixed to the pc board, ?t hermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint wi th the copper plane on the drain pins, the solder mask ge neration occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum pow er trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.196 5.0 0.2 88 7.3 0.050 1.27 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.0 88 2.25 0.2 88 7.3 0.050 1.27 0.0 88 2.25
application note 826 vishay siliconix www.vishay.com document number: 72606 22 revision: 21-jan-08 application note recommended minimum pads for so-8 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.172 (4.369) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.
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